Page 329 - Mechatronics with Experiments

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ELECTRONIC COMPONENTS FOR MECHATRONIC SYSTEMS 315
digital computer as having a CPU and a bus. Here we assume that the CPU includes the
microprocessor’s clock, the CPU, the memory (random access memory (RAM) and read-
only memory (ROM)). The bus is made of three main groups of digital lines: address bus
lines used to address devices and memory by the CPU, control bus lines used to indicate
whether the operation is a read or a write as well as used for interface handshaking signals
between CPU and I/O devices, and a data bus which carries the data between the CPU and
I/O devices (or memory). Let us assume that the CPU executes programmed instructions
to perform logic and I/O with the external devices.
The address decoder circuit of each I/O device uniquely specifies the address of
the I/O device on the bus. The data lines of the device are connected to the data bus of
the computer. Every device that the CPU communicates with (reads or writes) must be
addressed by the CPU first. A particular device is selected on the address bus via the
decoder of the device whose address has been placed on the address bus by the CPU. The
address number to which the decoder responds by turning its output ON is set by jumpers
or DIP switches which define whether or not each address bus line has an inverter or direct
connection.
The control bus of the computer is used to strobe the I/O device to process the data
bus information. When a read (input) or write (output) operation is performed by the CPU,
the following sequence of events are generated by the CPU at the machine instruction level:

1. The CPU places the address of the I/O device on the address bus. Only one device
decoder will provide an active output in response to a unique address in the address
bus.
2. The CPU places the data on the data bus for the write operation, and
3. The CPU turns on the OUT signal of the control bus to tell the I/O device that the
data is ready.
4. When the I/O device is given enough time to read (or signals the CPU that it is done
via a handshake line in the control bus), the OUT signal is dropped, and CPU goes
on with other operations.

For read (input) operations, the sequence of steps 2 and 3 are changed:

1. The CPU places the address of the I/O device on the address bus. Only one device
decoder will provide an active output in response to a unique address in the address
bus.
2. The CPU turns on the IN signal of the control bus to tell the I/O device it is ready to
read the data.
3. The CPU reads the data on the data bus, and
4. When the CPU is done (transfer the data to its registers from the data bus), it drops
the IN signal, and CPU goes on with other operations.

In process control applications, the output device is a set of D-type flip-flops connected
to discrete output lines or a D/A converter, and the input device is a set of R-S flip-flops
connected to discrete input lines or an A/D converter (Figure 5.49).

Example Figure 5.50 shows the interface between a digital computer data output line
and a relay. The digital data line is set high or low under software control. This controls the
opto-coupler, which then turns the transistor ON/OFF. The transistor powers the control
circuit to the relay coil. Once the relay coil is energized, its contact conducts the current in
the output circuit which may turn ON/OFF a device, such as a light or a motor. Notice that