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Figure 22: Demultiplexer operation
10.3 Parity Generators
A parity generator/checker is a logic circuit that is used to detect 1-bit errors in a message or during data
entry. There are two types of parity generators:
• Even parity generator
• Odd parity generator
In an even parity generator, the number of binary ones (1s) in a transmitted message must always be
even. If the number of binary ones (1s) in a transmitted message are odd then it is assumed that an error
occurred during data transmission or data entry. The even parity is generator is implemented on
Exclusive OR (XOR) gate.
Consider the example of generating an even parity logic circuit
Consider the message to be transmitted:
P bit X Y Z
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
The Pbit (parity bit) must be calculated using the XOR logic circuit as follows:
• If the number of binary ones (1s) is even then the P` is 0.
• If the number of binary ones (1s) is odd, then the Pbit is 1
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