Page 88 - Handout Digital Electronics
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If there was no error during transmission Cbit will be zero. This assumption is that there were no multiple
bit changes during transmission. This is because in parity bit check codes, if two more bits change their
statuses, that is from 0 to 1 and vice versa, the error will not be detected.
Cbit Pbit X Y Z
0 0 0 0 0
0 1 0 0 1
0 1 0 1 0
0 0 0 1 1
0 1 1 0 0
0 0 1 0 1
0 0 1 1 0
0 1 1 1 1
10.4 Generating Odd parity bit logic circuit
The same message will be used to generate the odd parity
Pbit X Y Z
1 0 0 0
0 0 0 1
0 0 1 0
1 0 1 1
0 1 0 0
1 1 0 1
1 1 1 0
0 1 1 1
Produce the pbit (odd) Boolean expression as follows:
pbit (odd ) = XYZ + XYZ + XYZ + XYZ
= X (YZ + YZ ) + X (YZ + YZ )
= X (Y Z ) + X (Y Z )
= X Y Z
From the Boolean expression, produce the logic circuit as shown below:
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