Page 95 - Handout Digital Electronics
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Inputs                        Outputs
                 D3     D2     D1     Do              Y1     Yo     V
                 0      0      0      0               x      x      0
                 0      0      0      1               0      0      1
                 0      0      1      x               0      1      1
                 0      1      x      x               1      0      1
                 1      x      x      x               1      1      1



            The x‟s in the truth table stand for don’t care conditions. Assume the inputs D0 – D3 (where D3 has the
            highest priority and do the least) are interrupt requests. If all the inputs have not issued any requests to
            the processor (D3-D0 = 0), what appears at Y1 and Yo does not matter and V = 0, meaning no requests
            have been issued by any device to the processor. If do issues an interrupt request the outputs Yo = 0 and
            Y1 = 0 indicating that input line 0 has issued an interruption request and V =1 indicating a request has
            been issued. If D1 input line issues an interrupt request, then it does not matter whether Do also issues
            an interrupt request because D0 has a lower priority than D1. The outputs at Y1 and Yo will indicate a
            binary one (01) meaning D1‟s request will be serviced but both D and D3 must be zeros. The same
            applies to D2 and D3. If D2 issues a request, it also does not matter whether D1 and D0 have requests,
            they will simply be ignored because both have lower priorities compared to D2. But D3 must be equal to
            0. If D3 issues a request then it does not matter where D2, D1, or Do also issued requests. They will be
            ignored because D3 has the highest priority.

            The major disadvantage of assigning priorities is that a device with higher priority may take a long time
            to  be serviced as  long  as it has requests to the processor whilst  those with  smaller priorities will be
            ignored.

            Consider the example below where D3 and D2 have both issued interrupt requests. It is clear from the
            propagated signals that D3‟s request has been acknowledged whilst D2‟s has been ignored
























            Figure 29: Priority encoder operation









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