Page 130 - GIGABYTE Service Manual-v3.0-110101

Chapter 8 Peripheral Functions

8.1 LAN Chip

PCI Express Bus Interface:
The RTL8111B-GR is compliant with PCI Express Base Specification Revision 1.0a,
and runs at a 2.5GHz Signaling rate with X1 link width, i.e., one transmit and one
receive differential pair. The RTL8111B-GR supports four types of PCI Express
messages: interrupt messages, error messages, power management messages, and

hot-plug messages.
01. Regulator & Reference: CTRL18: Regulator Control, TRL15: Regulator Control
RSET: External resistor reference.

02. Power: 3VDUAL, VCC3, AVDD18, VDD18, VDD15, AVDD33.
03. Power Management: -PCIE_WAKE: Power Management Event, ISOLATEB:
Used to isolate the RTL8111B-GR from the PCI Express bus.
04. Clock: SRCCLK_LAN,-SRCCLK_LAN: PCI Express Differential Clock Source:
100MHz (from Clock Generator) XTALI_P, XTALO_P: Crystal 25MHz.

05. Reset: -PFMRST2 PCI Express Reset from I/O IT8718)
06. Transceiver Interface: ML_OP, ML_ON: PCI Express Transmit Differential Pair,
ML_IP, L_IN: PCI Express Receive Differential Pair.

07. EEPROM: EECS, EESK, EEDI_AUX, EEDO
08. LEDs: LED_ACT_TXRX, LED_LINK100, LED_LINK1000
LAN Repair Steps

8.1.1 LAN Repair Steps

01. Visually inspect on components around LAN chip to check if any damage.
02. Touch LAN chip to check any heating damage.
03. Check LAN connector pin any bent inside port.

04. Check LAN chip pin and back side solder to see if any open.
05. Check BIOS CMOS LAN settings.
06. Verify LAN ID MAC Address correct or not. If wrong, correct it by HDD program.
07. Measure LAN port pin impedance by Multi-Meter with diode mode.

08. Measure LAN port pin signals by Scope.
09. Check LAN all Voltage, Clock, Reset (see signals list). (Regulator Voltage, OSC,
CLK Generator CLK)
10. Check all signals between LAN chip and S-B, include Capacitor (see block

diagram).Before change LAN Chip or S-B to make sure all steps are measured.

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