Page 26 - FUNDAMENTALS OF COMPUTER

26 Fundamentals of Computers NPP

the instruction register provides room for it. _| OmVm h¡ Vmo Cgo {ZX}e a{OñQ>a OJh XoVm h¡Ÿ& `h a{OñQ>a
After holding the binary form of the instruc- Wmo‹S>r Xoa Ho$ níMmV² {ZX}e H$mo CPU Ho$ {S>H$moS>a H$mo àXmZ
tion the register supplies the instruction code
to the decoding and machine cycle encoding H$aVm h¡Ÿ& {S>H$moS>a BgH$mo g_PH$a CU H$mo XoVm h¡Ÿ&
unit. The size of instruction register depends Amdí`H$VmZwgma CU {d{^ÝZ H§$Q´>mob {g¾b CËnÝZ H$aVm
upon a particular CPU. For example, 8085 has h¡ {Oggo {ZX}e _| Xem©`m H$m`© g§nÝZ hmoVm h¡Ÿ& O¡go,
an 8-bit instruction register. 8085 _| EH$ 8-{~Q> H$m B§ñQ´>ŠeZ a{OñQ>a hmoVm h¡Ÿ&
(e) Accumulator (e) EŠ`yå`yboQ>a
Accumulator register is used to hold the {OZ g§»`mAm| na H$m`© H$aZm h¡ CZ_| go EH$
operands for the ALU. In many microproces- gm_mÝ`V`m EŠ`yå`ycoQ>a a{OñQ>a _| OmVr h¡Ÿ& H$B©
sors, the result of operation is always placed in _mBH«$moàmogoga _| {H«$`mAm| Ho$ n[aUm_ ^r EŠ`yå`yboQ>a _|
the Accumulator. The status register or flag
register is modified in accordance with the aIo OmVo h¡Ÿ& âboJ a{OñQ>a `m ñQ>oQ>g a{OñQ>a EŠ`yå`yboQ>a
contents of accumulator. Ho$ A§Xa pñWV g§»`m go à^m{dV hmoVr h¢Ÿ&
(f) Program Counter (Instruction Pointer) (f) àmoJ«m_ H$mC§Q>a (BÝñQ´>ŠeZ nm°BªQ>a) (PC/IP)
(PC/IP) NPP
The program counter (PC) is a special pur- àmoJ«m‘ H$mCÝQ>a (PC) EH$ {deof H$m`© a{OñQ>a hmoVm
pose register which points to the next instruc- h¡ Omo CPU Ho$ Ûmam g§nÝZ hmoZo dmbo AJbo {ZX}e H$mo
tion to be executed by the CPU. That means, it ~VmVm h¡Ÿ& AWm©V² Bg a{OñQ>a _| AJbo {ZX}e H$m ES´>og
holds the address of the next instruction.
hmoVm h¡Ÿ&
The name “Program Counter” is confus- “àmoJ«m_ H$mC§Q>a“ eãX go Eogm bJVm h¡ O¡go `h H$moB©
ing because it is not used for any counting JUZm H$aVm hmo Ÿ& na§Vw Eogm Zht h¡Ÿ& My±{H$ `h EH$ _o_moar Ho$
purpose. Therefore other meaningful name for nVo H$s Amoa Bemam (nm°BªQ>) H$aVm h¡ AV… Bgo hr 'B§ñQ´>ŠeZ
it is ‘Instruction Pointer (IP)’. It helps the CPU
to keep track of the instructions. Whenever an nm°BªQ>a (IP)' ^r H$hm OmVm h¡ Ÿ& `h CPU H$mo _o_moar go
instruction is fetched by the CPU the contents B§ñQ´>ŠeZ boZo _| _XX H$aVm h¡ Ÿ& O¡go hr _o_moar go H$moB©
of PC are automatically incremented to point {ZX}e CPU _| AmVm h¡ ñdV… PC Ho$ A§Xa H$s g§»`m
to the next instruction. When a branching in- n[ad{V©V hmoH$a AJbo {ZX}e H$s Amoa Bemam H$aZo bJVr h¡Ÿ&
struction is executed the address of next in- bo{H$Z O~ H$moB© ~«mpÝM¨J (emIm-g§~§{YV) {ZX}e XoVo h¢ Vmo
struction is automatically placed onto the stack. ñQ>oH$ H$m Cn`moJ H$aHo$ PC Ho$ A§Xa Ho$ ~mBZar Z§~a H$mo
Microprocessor 8085 has a 16 bit program ñQ>oH$ na nwe H$a XoVo h¡Ÿ& dmng AmZo na Bgr H$mo nm°n H$a
counter (PC) and 8086/88 has IP. boVo h¡Ÿ& 8085 _mB©H«$moàmogoga _| 16-{~Q> H$m PC h¡ VWm
8086/88 _| ^r 16-{~Q> H$m IP h¡Ÿ&
(g) Flag Register (Status Register) (g) âboJ a{OñQ>a (ñQ>oQ>g a{OñQ>a)
The flag register contains conditional bits Bg a{OñQ>a Ho$ A§Xa H$ÊS>reZb {~Q²>g hmoVr h¡ Omo
which are either set or reset as per the result. In n[aUm‘ Ho$ AZwgma ¶m Vmo goQ> `m [agoQ> hmoVr h¡ Ÿ& nyar
this register the individual bits are important. ~mBZar g§»`m _hËdnyU© Z hmoH$a AbJ-AbJ {~Q²>g
For example, flag bits are there to show carry,
_hËdnyU© hmoVr h¢Ÿ& `o g^r {~Q²>g n[aUm_ H$s pñW{V`m±